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Utilizing Timing Error Detection and Recovery to Dynamically Improve Superscalar Processor Performance: SPRIT3E
Category(s):
For Information, Contact:
Jay Bjerke
Commercialization Manager, Engineering
515-294-4740
licensing@iastate.edu
Web Published:
5/8/2015
ISURF #
3421
Summary:
ISU researchers have developed a method that enables modern high performance computer processors to operate reliably at speeds higher than previously possible.

Development Stage:
Description:
Modern processors (and in fact all synchronous logic circuits) use a clock to control execution of the circuit. The speed of this clock, which in large part determines how quickly the processor runs applications, is traditionally limited by worst case delay. The resulting propagation delay is difficult to determine precisely for three main reasons. First, variations induced when computer chips are produced create variable delays in the chips. Second, variations in environmental conditions during operation, such as temperature and voltage, affect the delay through the circuit. Finally, although it is possible to find the longest paths through the logic, it is not known how often the input combinations given during operation will use these paths. To avoid timing errors, traditional design assumes worst case values for these factors, giving an overly high delay estimate, and causing the clock period to be set too slow. To overcome this limitation and increase clock speed, ISU researchers have developed SPRIT3E (Superscalar PeRformance Improvement Through Tolerating Timing Errors). By applying fault tolerance combined with dynamic control theory, this technique performs error detection and correction, and allows clock speeds to scale farther, which in turn lets applications finish earlier. In addition, this method may be applied to any modern processor, since the limitation it overcomes is applicable to all synchronous logic circuits.

Advantage:
• Enables processors to reliably execute applications faster than previously possible
• Performs both error detection and correction (unlike the closest competitor, which performs only error avoidance)
• May be applied to any modern processor, since it overcomes the limitation of the worst case delay assumption that places a minimum on the clock period of modern digital circuits
Application:
High performance processor design; synchronous logic circuit design

Patent Information:
*To see the full version of the patent(s), follow the link below, then click on "Images" button.
Country Serial No. Patent No. Issued Date
United States 12/107,415 7,671,627* 3/2/2010


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