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ChainMap: Depth-Optimal Mapping of Logic Chains in Reconfigurable Fabrics
Category(s):
For Information, Contact:
Jay Bjerke
Commercialization Manager, Engineering
515-294-4740
licensing@iastate.edu
Web Published:
5/7/2015
ISURF #
3631
Summary:
Iowa State University researchers have developed ChainMap, an algorithm that optimally maps logic chains used in Field Programmable Gate Arrays (FPGA) to improve their performance

Development Stage:
The algorithm is available for testing

Description:
Look-up table (LUT)-based FPGA have typically been used in prototyping rather than as critical design elements.  However, performance improvements have advanced FPGAs to being valuable in development of end-components.  An important dedicated structure found in currently available architectures is the arithmetic carry chain.  However, in designs that incorporate limited arithmetic operations and contain a carry-select style architecture, the carry chain is an under utilized resource.  To overcome this deficiency, ISU researchers have developed a novel algorithm, ChainMap, for depth-optimal mapping of logic chains in reconfigurable fabrics.  ChainMap establishes a difference between programmable routing connections and chain connections, and optimally identifies them without requiring the use of a user-specified hardware description language (HDL).  In addition, ChainMap allows the use of non-arithmetic as well as arithmetic chains. As a result, significant performance gains are achievable for all designs and design flow is freer.

Group:
A license to related ISURF technology ISURF #3630, Logic Element Architecture for Improving Logic Chain Operations in Programmable Devices, will also be required for commercial use
Advantage:
• Effective (experimental results indicate that ChainMap improves performance up to 40% compared to HDL methods)
• Efficient (allows the use of non-arithmetic operations and does not require the preservation of HDL macros through the design flow)
• Flexible (eliminates the need for HDL to create logic chains and frees the design flow)
References:
Patent Information:
*To see the full version of the patent(s), follow the link below, then click on "Images" button.
Country Serial No. Patent No. Issued Date
United States 12/236,781 8,661,394* 2/25/2014


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