Logic Element Architecture for Improving Logic Chain Operations in Programmable Devices
For Information, Contact:
Jay Bjerke
Commercialization Manager, Engineering
Web Published:
Iowa State University researchers have developed a logic element architecture that simplifies generic logic chain operations and improves the functionality of each logic element in programmable devices.

Development Stage:
The logic element architecture is available for demonstration, and ISU is seeking partners interested in commercializing this technology

Reconfigurable fabrics are an important element of reconfigurable computing—systems architecture that offer both performance and flexibility for a broad range of applications—and typically depend on Field Programmable Gate Arrays (FPGA) which contain programmable logic that allows them to be configured by the designer or customer after manufacturing.  However, compared with application-specific integrated circuits (ASIC), FPGA have lower performance and require increased power consumption.  To overcome some of these drawbacks, ISU researchers have developed a logic element architecture for generic logic chains in programmable devices.  In contrast to  architectures to support arithmetic operations that are characterized by the computation of two (K-1)-input Boolean functions with identical inputs with one carry chain and one programmable routing output, the generic logic chain architecture supports traditional logic element arithmetic operation as well as allows a single K-input Boolean function to be computed and output to both the carry chain and programmable routing outputs.  This allows both arithmetic and non-arithmetic operations to be grouped together as generic logic chain operations and use the full K-input functionality of each logic element.  Since one feature of this logic element is that it makes no distinction between arithmetic and non-arithmetic operations, it makes it possible for circuits that contain no arithmetic operations to use the existing carry chain connection for performance improvement.

A license to related ISURF technology ISURF #3631, ChainMap: Depth-Optimal Mapping of Logic Chains in Reconfigurable Fabrics, will also be required for commercial use.

• Effective (enables carry chain reuse, improving design performance at minimal cost)
• Robust (increases maximum clock frequency by 47% in technology map experiments while reducing utilized routing resources by 13%)
• Efficient (avoids the use of extraneous interconnects since only one wire is needed compared to approaches that require a standard carry chain connection and an additional connection between logic elements)
Patent Information:
*To see the full version of the patent(s), follow the link below, then click on "Images" button.
Country Serial No. Patent No. Issued Date
United States 12/237,076 8,438,522* 5/7/2013

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